RLCK Extraction and Simulation in High-Speed SoC Designs (Tutorial Abstract)

The first part of this tutorial will examine the present “infrastructure” of MOS modeling for circuit simulation, with particular emphasis on how history has played a role at least as large as that of engineering. The viewpoint will be that of an analog design “consumer” of MOS models who must make the best possible use of a badly flawed infrastructure. In recent years, the entire structure of MOS models has been evolving into continually more complicated and empirical forms, opening up a “reality gap” between a model’s mathematical structure and circuit design usage. The need for extensive model “binning” to provide accuracy over a large range of channel geometry is causing present-day MOS models to more closely approach tablelookup methods, rather than a design-useful description of the underlying MOS technology. Among the many severe consequences of the present situation, the MOS models have become completely removed from good circuit design practices, particularly for analog design; many common analog circuits cannot even be simulated properly using “modern” MOS models! The final part of this tutorial will describe a new direction for MOS modeling, based on the use gms/Id over the range weak, moderate, and strong inversion. This approach provides a more modern grounding for understanding the MOSFET, and also leads directly into simple and powerful techniques for effective analog circuit design using modern deep-submicron technology.